Skip to content
CONNEXUSCONNEXUS
  • CORPORATE
    • ABOUT US
    • PARTNERS
    • RESOURCES
  • PRODUCTS & SERVICES
    • TECHNOLOGY
    • PRODUCTS
    • SERVICES
  • SUSTAINABILITY
  • CAREERS
  • CONTACT US

Author Archives: Max V

Memory Compiler IP Design Features

Common Design Features: Bit-write Output Registered Bypass Mode BIST Mux Scan Enable Scan Flops Timing...

Memory Compiler IP EDA Views

Documentation: Memory Description Document (MDD) Customer Application Note (CAN) Datasheet Document (DSD) Memory Compiler Generator...

NPU Design Framework

The Neural ASIC Design Framework is a sophisticated platform designed to facilitate the development of...

  • 1
  • 2
  • 3
  • 4
  • …
  • 13

Industry

Events Blog News

Thrilled to announce Connexus is now part of the NVIDIA Inception Program

Events Blog News

Connexus at #ICOS2026 | Strengthening Industry-Academia Collaboration

Events Blog

Connexus Academy – Our Internal Training Domain

Events Blog News

Building Global Innovation Bridges: Vietnam x Germany 

Events Blog News

CNX Seminar @ VKU Job-Fair 2025 – Inspiring the Next Generation of Silicon Warriors!

Blog

Connexus Proud to Contribute to Vietnam’s Tech Future

Events Blog News

Connexus: Presents Our Chip R&D Demo and Welcomes General Secretary To Lam

Blog News

Great News for Connexus
About Us
Partners
Products
Services
Sustainability
Careers
Contact Us
Resources
Privacy Policy
Terms of Service
Copyright 2023 © CONNEXUS, All rights reserved.
  • CORPORATE
    • ABOUT US
    • PARTNERS
    • RESOURCES
  • PRODUCTS & SERVICES
    • TECHNOLOGY
    • PRODUCTS
    • SERVICES
  • SUSTAINABILITY
  • CAREERS
  • CONTACT US