JOB DESCRIPTION
POSITION: ASIC/SoC Physical Design/Back-End Lead
Updated: AUG – 2025
Location: Ho Chi Minh city, Vietnam
About Connexus:
Connexus is a fast-growing fabless semiconductor startup focused on AI chips and advanced chip design services. We aim to empower the next generation of AI workloads with cutting-edge technologies, while building a collaborative, innovative, and people-first culture.
Role overview:
Lead the full chip implementation from RTL to GDSII, driving PPA excellence and successful tape-outs. Mentor the team, optimize design flows, and collaborate across functions to deliver cutting-edge AI and semiconductor solutions.
Key Responsibilities:
- Own the physical design flow (RTL → GDSII) for AI accelerator chips.
- Drive PPA (Power, Performance, Area) optimization for AI workloads.
- Perform floor-planning, power planning, STA, CTS, routing, DRC/LVS, SI and noise analysis.
- Execute sign-off for timing, DRC, LVS, and power analysis.
- Develop and maintain APR scripts and back-end design methodologies.
- Evaluate and improve EDA tools, flows, and automation.
- Lead/Mentor the physical design team, including junior engineers and trainees.
- Contribute to R&D and continuous improvement of Connexus’ ASIC design methodology.
Requirements:
- Bachelor’s or master’s degree in Electronics Engineering, Telecommunication, Physics, or related fields.
- Preferred more than 7 years’ experience in ASIC Back-End Design Engineering.
- Hands on experience with detailed exposure to an actual SoC physical design in STA, Floor-Planning, Power Analysis, CTS, Routing, DRC/LVS and Noise Analysis using Magma or Synopsys ASIC physical design tools.
- Excellent analytical and problem-solving skills along with attention to details.
- Scripting language with Perl, Tk/Tcl, AWK, Shell scripting a very big asset. Strong communication, documentation, and analytical skills.
- Good English communication skills.
- Strong team player, self-motivated, humble, honest, and willing to learn
Preferred Skills:
- Experience in using and optimizing EDA tools.
- Knowledge of advanced process technologies and layout verification methodologies.
Benefits:
- Competitive salary, performance bonuses, and retention schemes.
- Private health insurance for employees and dependents.
- Learning and growth opportunities, guided by top industry experts.
- Join a fast-paced startup environment with impactful projects shaping the semiconductor future
Apply via email: job@connexus.vn