POSITION: Fresher Front End SoC 

Location: Ho Chi Minh city, Vietnam 

 

About Connexus:  

Connexus is a fast-growing fabless semiconductor startup focused on AI chips and advanced chip design services. We aim to empower the next generation of AI workloads with cutting-edge technologies, while building a collaborative, innovative, and people-first culture. 

 

Key Responsibilities: 

  • Develop and verify RTL blocks for SoC front-end design using Verilog / SystemVerilog 
  • Write simulation testbenches, run functional verification, and debug waveform results 
  • Use VCS and DVE for simulation, debug, and result analysis 
  • Support FPGA prototyping and design validation using Vivado 
  • Participate in micro-architecture discussions, design reviews, and technical problem-solving 
  • Learn and apply front-end design concepts such as clocking, reset, FSM, pipeline, and CDC basics 
  • Review synthesis, timing, and area results with guidance from senior engineers 
  • Work with both commercial and open-source front-end tools where appropriate 
  • Document design assumptions, implementation notes, and verification results 
  • Collaborate closely with senior RTL engineers on real project development and tape-out related activities 

 

Requirements: 

  • Final-year student or recent graduate in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field 
  • At least 6 months of relevant working experience 
  • Hands-on experience with Verilog or SystemVerilog through coursework, university labs, or personal projects 
  • Basic understanding of RTL design, simulation, waveform debugging, and testbench development 
  • Familiarity with front-end development tools such as:  
  • Vivado 
  • VCS / DVE 
  • Open-source tools such as Verilator, GTKWave, Icarus Verilog, or Yosys are a plus 
  • Basic understanding of timing concepts, clock domains, reset behavior, and pipelined design 
  • Able to read technical documentation and communicate clearly in an engineering environment 
  • Willingness to learn from hands-on work with real semiconductor development flows 

 

Nice to have:  

  • Academic or personal project experience in FPGA, RTL design, or digital systems 
  • Basic scripting knowledge in Python, Tcl, or Shell 
  • Interest in SoC design, ASIC front-end flow, FPGA, or AI hardware 

 

     Why join Connexus:: 

  • Competitive salary based on capability 
  • Private medical insurance. 
  • Mentorship from top industry experts 
  • Comprehensive CNX Academy training 

 

 

Working address: 5th Floor, Hado South Building, 60 Truong Son Str., Tan Son Hoa Ward, Ho Chi Minh City, Vietnam 

 

Apply via email: job@connexus.vn